The present invention relates generally to software for designing integrated circuits and more specifically to a technique to simplify the schematic of a Register Transfer Level (RTL) netlist.
A typical design cycle for an integrated circuit, referred to as compilation, starts with an extraction phase, followed by a logic synthesis phase, and, depending upon the target hardware architecture, either a layout phase or fitting and assembly phases.
In addition to implementing their desired functions, designs typically must satisfy one or more additional design goals, such as operating speed, power consumption, and/or programmable device resource consumption. Typically, the predicted performance of a design with respect to one or more design goals is determined through simulation or analysis following a phase of the compilation. The designer can evaluate the predicted performance of the design and decide to either accept the results of the compilation or modify the design to improve its predicted performance, and hopefully its actual performance as well.
Visualization applications assist designers in evaluating predicted performance of a design. Visualization applications present predicted performance information of a design in a number of different graphical and text formats. Using visualization applications, designers can identify portions of the design that do not satisfy design goals. Visualization applications may also help designers identify portions of the design that can be improved to meet or exceed design goals.
Many typical digital designs include a number of registers. Each register is capable of storing one or more bits of data. Registers are often connected together via combinatorial logic. In many cases, the set of connections between two or more registers includes a large number of paths, each connecting one bit of a source register with one or more bits of at least one destination register. For example, there are up to 256 different paths between two 16 bit registers.
Visualization applications typically present predicted performance information on a path level view. These visualization applications annotate each path with its predicted performance information. As a result, designers tend to focus their optimization efforts on improving the performance of individual paths. However, the performance of paths connected with the same registers often are interrelated. Thus, when a designer improves the performance, such as the timing, of one path between registers, the performance of another path between these registers may get worse. In these situations, the designer merely shifts a problem to different paths, rather than finding a solution that improves the performance of the overall design. This problem can occur in any type of integrated circuit design and is especially frequent with programmable devices such as field programmable gate arrays, which route all of the paths between source and destination registers independently.